This seminar will consider how to use processors with multiple cores in a way that safety can be assured, and such that the resulting system can be certified against industry standards and guidelines.

(A multi-core processor is typically made of several independent processor cores on the same chip, connected through an on-chip bus. Manycore processors are specialist multi-core processors designed for a high degree of parallel processing, containing a large number of simpler, independent cores (from a few tens of cores to thousands or more). Manycore processors are used extensively in embedded and high-performance computing.)

This seminar will be held in central London.

Speakers include:

Iain Bate, University of York - "Multi-core architectures and timing analysis: Their influence on the scheduling of certifiable real-time systems"

TBC, Lynx Software Technologies - TBC

Guillem Bernat, Rapita Systems - “Independently Verifying the effectiveness of RTOS Hypervisors at reducing Multicore Interference”

Olivier Charrier, Wind River - TBC

Mark Headley and Mike Standish, Dstl - "A strategy for Multi-Core Qualification"

Further details TBA.