Multi-core and many-core devices are the norm in mainstream embedded systems. There has been restricted use in some automotive systems but for avionics few (if any) such devices have featured in deployed systems. There is currently only one Position Paper (CAST-32A) to provide guidance on their safe design, implementation and assurance, which is in the process of being formalised by EASA and the FAA into an Acceptable Means of Compliance. In this paper, we will evidence why some practices might change and identify some significant open challenges for both industry and academia, with the aim of identifying key areas where further work is required and providing discussion on how that work might be progressed. The majority of published work on multi-core and many-core focuses on the issues of bounding predictability; i.e. performing analysis to understand how the behaviour of the device can be expected to present within a particular context; often developed as a ‘timing analysis’; this is not new. While there are differences in the timing analysis required to support a multi-core and many-core assessment, the avionics industry has mature processes for dealing with timing at all levels of integrity. This paper places such timing analysis within the context of a safety argument for multi-core and manycore in safety-critical applications and the application. The paper describes some associated shortfalls of current standards and guidance, particularly for incremental certification. The context of this paper is multi-core (i.e. more than one core), many-core (e.g. more than 64 cores) and Multi-Processor System on Chip (MPSoC).