Creating a multi-core platform for safety-critical avionics is the next major step for most avionics manufactures. While multi-core processors are commonly used in most other markets, the avionics industry has taken years to trust multi-core technologies. Acceptance has been slow due to an avionics system’s stringent safety and deterministic requirements. As a result, years of study have been invested by certification authorities and industry suppliers to identify the issues multi-core processors pose for safety-critical systems. Formalized positions of these efforts are the FAA CAST-32A Positioning Paper, and EASA’s multi-core Certification Review Item (CRI). The crux of these papers (regarding software) focuses on bounding and controlling the interference patterns that exists when processor cores share resources. This paper highlights the challenges of implementing multi-core processors for avionics developers. It will present Deos SafeMCTM and show how it helps address CAST-32A objectives by utilizing unique operating system features designed for minimizing and bounding contention issues within multi-core environments. Features such as cache partitioning, memory pooling and safe scheduling enable the user to configure the memory architecture to minimize cache thrashing and schedule applications across all cores. Further, most of these Deos features are processor agnostic which allows system developers to pick more current and best suited processor technologies. Together, these capabilities enable developers to employ modern systems that orchestrate software applications such that conflicts over shared resources are minimized and the overall performance advantages of multicore processors can best be utilized.